Advanced area array packaging - from CSP to WLP

Chip scale packages (CSP) evolved from the design concept of ball grid array (BGA) packages and are becoming the integrated circuit (IC) packaging of choice for many small form-factor electronics products. One area of their increasingly wide adoption is for applications in flash, SRAM (static random access memory), and DRAM (dynamic random access memory) memory devices. The next step of packaging advancement is moving toward the wafer level packages (WLP) that reduce the package sizes to chip size packages. This paper reviews and discusses the design of a number of selected CSP and WLP technology advancement, their applications and advantages; the main focus of their applications being for the memory devices. Also included is the design consideration of CSP and WLP in three-dimensional (3-D) stacking assemblies to achieve high density and capacity in memory modules.