Power-Performance Optimal DSP Architectures and ASIC Implementation

A hierarchical, sensitivity-based ASIC design methodology is proposed and demonstrated in the implementation of power-performance optimal signal processing kernels for wireless applications. The design approach uses a systematic exploration of the power-performance design tradeoff space at the architecture, micro-architecture, and circuit levels. Energy-efficiency gains achieved via this methodology are exploited to accommodate flexibility to support multi-standard radio architectures. The methodology is exemplified in the selection of architecture and design of a flexible digital finite impulse response (FIR) filter. The flexible FIR filter consumes area and power that is only 2 to 4 times that of a dedicated ASIC FIR.