Technology Driven DSP Architecture Optimization within a High-Level Block Diagram Based Design Flow

In the process of designing adaptive wireless communication systems, the design cycle traditionally requires re-entering a design at various abstraction levels, constraining the implementation choices and increasing time-to-market. An approach to use a unified design description for algorithm verification and architecture exploration is presented. The proposed graphical block-based design entry and re-targetable design flow provide the ability to track technology features in the process of architecture selection. Using this approach, word length optimization, register retiming, and data-stream interleaving are applied to square-root algorithm to reduce power and area. The flow is demonstrated on a complex multi- antenna signal processing. An example of Sobel edge detection illustrates the integration of IP macros and hardware emulation.