Performance analysis of the memory hierarchy via Markov chains and state cloning

The performance of the memory hierarchy currently plays an important role in the design of computer systems. Most computers today, from micros to mainframes, utilize cache memory to increase overall system performance. Parallel processing systems sometimes use cache memory to allow all processors to share the same address space. Even super computer design is influenced by the performance of the memory hierarchy. This dissertation presents an innovative approach to the performance evaluation of hierarchical memory systems. Traditional evaluation techniques of such systems employ simulation. Simulation is often expensive because it is extremely time consuming and requires much disk space. An alternative approach, through the use of Markov Chains and state cloning techniques, is presented in this dissertation. The memory hierarchy is explained and a performance model is developed. This performance model is applied to traditional cache memory. Shared memory in parallel processing systems is presented along with the concerns of memory coherency. Memory coherency protocols are given and the newly developed performance model is used to measure and to compare the efficiency of the given protocols.