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Compiler-Directed Cache Line Size Adaptivity

Dan Nicolaescu, Xiaomei Ji, Alex V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta

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Abstract

Abstract. The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is xed at design time. Miss rates for di erent applications can be improved if the line size could be adjusted dynamically at run time. We propose a system where the compiler can set the cache line size for di erent portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing. 1

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What this paper is about

Abstract. The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is xed at design time. Miss rates for di erent applications can be improved if the line size could be adjusted dynamically at run time. We propose a system where the compiler can set the cache line size for di erent portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing. 1

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Available abstract

Abstract. The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is xed at design time. Miss rates for di erent applications can be improved if the line size could be adjusted dynamically at run time. We propose a system where the compiler can set the cache line size for di erent portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing. 1

Key concepts: Computer science, Cache, Compiler, Parallel computing, CPU cache, Optimizing compiler, Cache algorithms, Cache pollution

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