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Formal methods and verification
K. McEvoy, John Vivian Tucker
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Abstract
This part describes three different approaches to the use of formal methods in the verification and design of systems and circuits. Chapter 2 describes the stages involved in the verification of a counter using a mechanized theorem prover. The next chapter describes a mathematical model of synchronous computation within which formal transformations which are useful in the design process can be defined. Chapter 4 describes verification in a different framework – that of the algebra of communicating processes.