2015Unpublished venueRequires access

LVDS transmitter with optimized high power-efficiency 8:1 MUX

Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye, Junyan Ren

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Abstract

This paper presents an optimized high power-efficiency 8:1 multiplex (MUX) in a low voltage differential signaling (LVDS) transmitter, which is capable of transmitting data rate of 8Gb/s fabricated in a 65nm CMOS process. As compared with a conventional tree-type 8:1 MUX, the proposed 8:1 MUX saves 53.8% power consumption. A conventional single-stage MUX seldom achieves a high-speed data rate as high as 8Gb/s because of its large parasitic loading at output node. The power consumption of this LVDS transmitter is 11mW under a 1.2 V supply voltage.

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What this paper is about

This paper presents an optimized high power-efficiency 8:1 multiplex (MUX) in a low voltage differential signaling (LVDS) transmitter, which is capable of transmitting data rate of 8Gb/s fabricated in a 65nm CMOS process. As compared with a conventional tree-type 8:1 MUX, the proposed 8:1 MUX saves 53.8% power consumption. A conventional single-stage MUX seldom achieves a high-speed data rate as high as 8Gb/s because of its large parasitic loading at output node. The power consumption of this LVDS transmitter is 11mW under a 1.2 V supply voltage.

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Available abstract

This paper presents an optimized high power-efficiency 8:1 multiplex (MUX) in a low voltage differential signaling (LVDS) transmitter, which is capable of transmitting data rate of 8Gb/s fabricated in a 65nm CMOS process. As compared with a conventional tree-type 8:1 MUX, the proposed 8:1 MUX saves 53.8% power consumption. A conventional single-stage MUX seldom achieves a high-speed data rate as high as 8Gb/s because of its large parasitic loading at output node. The power consumption of this LVDS transmitter is 11mW under a 1.2 V supply voltage.

Key concepts: Transmitter, Multiplexer, CMOS, Multiplex, Voltage, Node (physics), Electronic engineering, Power (physics)

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