A 5.6 nV/ $\surd $ Hz Chopper Operational Amplifier Achieving a 0.5 $\mu$ V Maximum Offset Over Rail-to-Rail Input Range With Adaptive Clock Boosting Technique
Yoshinori Kusuda
Abstract
Yoshinori Kusuda
Abstract
This paper presents a standalone 5.6 nV/√Hz chopper op-amp that operates from a 2.1-5.5 V supply. Frequency compensation is achieved in a power-and area-efficient manner by using a current attenuator and a dummy differential output. As a result, the overall op-amp only consumes 1.4 mA supply current and 1.26 mm2 die area. Up-modulated chopper ripple is suppressed by a local feedback technique, called auto correction feedback (ACFB). The charge injection of the input chopping switches can cause residual offset voltages, especially with the wider switches needed to reduce thermal noise. By employing an adaptive clock boosting technique with NMOS input switches, the amount of charge injection is minimized and kept constant as the input common-mode voltage changes. This results in a 0.5 μV maximum offset and 0.015 μV/°C maximum drift over the amplifier's entire rail-to-rail input common-mode range and from -40 °C to 125 °C. The design is implemented in a 0.35 μm CMOS process augmented by 5 V CMOS transistors.
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This paper presents a standalone 5.6 nV/√Hz chopper op-amp that operates from a 2.1-5.5 V supply. Frequency compensation is achieved in a power-and area-efficient manner by using a current attenuator and a dummy differential output. As a result, the overall op-amp only consumes 1.4 mA supply current and 1.26 mm2 die area. Up-modulated chopper ripple is suppressed by a local feedback technique, called auto correction feedback (ACFB). The charge injection of the input chopping switches can cause residual offset voltages, especially with the wider switches needed to reduce thermal noise. By employing an adaptive clock boosting technique with NMOS input switches, the amount of charge injection is minimized and kept constant as the input common-mode voltage changes. This results in a 0.5 μV maximum offset and 0.015 μV/°C maximum drift over the amplifier's entire rail-to-rail input common-mode range and from -40 °C to 125 °C. The design is implemented in a 0.35 μm CMOS process augmented by 5 V CMOS transistors.
Key concepts: Mathematics, Notation, Arithmetic