Low power data-driven dynamic logic circuits

Dynamic Logic is used in high performance circuit designs for its high speed and less \n \ntransistor needed to implement a same function compared to Static Logic. \n \nData-Driven Dynamic Logic utilizes input data to replace clock signal as control of \n \npre-charge and evaluation phase. By elimination the clock, less power consumption \n \ncan be obtained without speed degradation. In this project, Data-Driven Dynamic \n \nLogic is undertaken to design CMOS circuits concentrating on power and speed \n \nperformance. Full Adders are designed with D3L technique and Domino, NP-CMOS \n \ncircuit techniques to compare the performance trade-offs. 4-bit Ripper Carry Adder, \n \n4-bit Kogge-Stone Adder and 16-bit Kogge-Stone adder are also implemented and \n \nsimulated using Cadence Virtuoso software. The results show that Data-Driven \n \nDynamic Logic circuits are able to work under low supply voltage. For simple basic \n \nlogic, D3L logic may save power at the cost of longer pre-charge time. When \n \nData-Driven Driven Dynamic Logic is applied to 16-bit Kogge-Stone Adder, the \n \nadvantage becomes evident that it is 13% faster and the power consumption is 15% \n \nlower.