An FPGA-based MPSoC for real-time ECG analysis
El Hassan El Mimouni, Mohammed Karim, Mohamed‐Yassine Amarouch
Abstract
El Hassan El Mimouni, Mohammed Karim, Mohamed‐Yassine Amarouch
Abstract
We have developed - and present in this article - a Master-Slave Multiprocessor System on Chip (MPSoC) for ECG analysis; it is based on Field Programmable Gate Array (FPGA). More exactly, it is a 3-processor MPSoC, where in principle, on one hand 2 slaves deal with some analysis of the signals of the 12-lead ECG standard and on another hand a master controls and coordinates the whole system. The Xilinx soft processor MicroBlaze is used as elementary processor and the 2 slaves communicate with the master by means 2 mailboxes via PLB bus. Due to the limited features of the available board at the time of experimentations, namely the Nexys 3 from Digilent featuring Xilinx SPARTAN 6 XC6SLX16 FPGA device, only a reduced software is tested, successfully, with the local memory of the used FPGA board. We have used different ECG signals from Physiobank databases for this qualitative evaluation of the proposed system. To our knowledge, this MPSoC implementation is novel, authentic and scalable.
OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
We have developed - and present in this article - a Master-Slave Multiprocessor System on Chip (MPSoC) for ECG analysis; it is based on Field Programmable Gate Array (FPGA). More exactly, it is a 3-processor MPSoC, where in principle, on one hand 2 slaves deal with some analysis of the signals of the 12-lead ECG standard and on another hand a master controls and coordinates the whole system. The Xilinx soft processor MicroBlaze is used as elementary processor and the 2 slaves communicate with the master by means 2 mailboxes via PLB bus. Due to the limited features of the available board at the time of experimentations, namely the Nexys 3 from Digilent featuring Xilinx SPARTAN 6 XC6SLX16 FPGA device, only a reduced software is tested, successfully, with the local memory of the used FPGA board. We have used different ECG signals from Physiobank databases for this qualitative evaluation of the proposed system. To our knowledge, this MPSoC implementation is novel, authentic and scalable.
Key concepts: MPSoC, Field-programmable gate array, MicroBlaze, Computer science, Embedded system, Scalability, Multiprocessing, System on a chip