Implementation of Turbo Decoder Based on Two-step SOVA with a Scaling Factor

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.