Low-area FFT Processor Structure using Radix-4^2 Algorithm

In this paper, a low-area FFT structure using algorithm is proposed. The large point FFT structure consists of cascade connection of the many stages. In implementation of large point FFT using algorithm, stages which number of different coefficients are only 3 appear in every 2 stages. For example, in the 4096-point FFT, the stages that number of different coefficients are 3 appear in stage 1, 3, and 5 among 6 stages. Multiplication block area of these 3 stages can be reduced using CSD(Canonic Signed Digit) and common sub-expression sharing techniques. Using the proposed structure, the 256-point FFT is implemented with the Verilog-HDL coding and synthesized by cell area in tsmc CMOS library. This result shows 23% cell area reduction compared with the conventional structure.