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2006•Unpublished venueRequires access

A Security Software Development Methodology Using Formal Verification Tools

Seung-Ju Jang

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Abstract

This paper suggests method of safe security S/W by verifying and its result of formal verification tool. We will survey many formal verification tools and compare features of these tools. And we will suggest what tool is appropriate and methodogoly of developing safe security S/W. The Z/EVES is the most appropriate tool. This paper proposes formal verification of ACS by using RoZ tool which is formal verification tool to create UML model. The specification and verification are executed using Z/EVES tool. These procedures can find weak or wrong point of developed S/W.

About this research paper

What this paper is about

This paper suggests method of safe security S/W by verifying and its result of formal verification tool. We will survey many formal verification tools and compare features of these tools. And we will suggest what tool is appropriate and methodogoly of developing safe security S/W. The Z/EVES is the most appropriate tool. This paper proposes formal verification of ACS by using RoZ tool which is formal verification tool to create UML model. The specification and verification are executed using Z/EVES tool. These procedures can find weak or wrong point of developed S/W.

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Available abstract

This paper suggests method of safe security S/W by verifying and its result of formal verification tool. We will survey many formal verification tools and compare features of these tools. And we will suggest what tool is appropriate and methodogoly of developing safe security S/W. The Z/EVES is the most appropriate tool. This paper proposes formal verification of ACS by using RoZ tool which is formal verification tool to create UML model. The specification and verification are executed using Z/EVES tool. These procedures can find weak or wrong point of developed S/W.

Key concepts: Computer science, Formal verification, Formal methods, Verification, Software verification, Software engineering, Intelligent verification, Formal specification

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