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2008•International Journal on Intelligent Electronic SystemsOpen access

TECHNIQUES FOR GLITCH POWER REDUCTION IN CMOS VLSI CIRCUITS

G. Sathiyabama, J. Raja

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Abstract

The dynamic power dissipation is the dominant source of power dissipation in CMOS circuits.It is directly related to the number of signal transitions and glitches.The glitches occupy a considerable amount of power of the total power dissipation in CMOS circuits.This paper presents a survey of the different techniques used for decreasing the dynamic power by reduction of glitches.The advantages and limitations of these techniques are also discussed.Glitches, CMOS circuits, low power, path balancing, gate sizing.

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The dynamic power dissipation is the dominant source of power dissipation in CMOS circuits.It is directly related to the number of signal transitions and glitches.The glitches occupy a considerable amount of power of the total power dissipation in CMOS circuits.This paper presents a survey of the different techniques used for decreasing the dynamic power by reduction of glitches.The advantages and limitations of these techniques are also discussed.Glitches, CMOS circuits, low power, path balancing, gate sizing.

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Available abstract

The dynamic power dissipation is the dominant source of power dissipation in CMOS circuits.It is directly related to the number of signal transitions and glitches.The glitches occupy a considerable amount of power of the total power dissipation in CMOS circuits.This paper presents a survey of the different techniques used for decreasing the dynamic power by reduction of glitches.The advantages and limitations of these techniques are also discussed.Glitches, CMOS circuits, low power, path balancing, gate sizing.

Key concepts: Glitch, CMOS, Very-large-scale integration, Electronic engineering, Reduction (mathematics), Electronic circuit, Computer science, Electrical engineering

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TECHNIQUES FOR GLITCH POWER REDUCTION IN CMOS VLSI CIRCUITS — Research Paper | ScholarLens