Zeng Da-fu
Abstract
Chip scale package (CSP) for flip-chip on hard substrates and wafer re-distribution is studied, and its process flow is described. Key technologies for CSP, such as structure designing, solder bumping, enveloping, and testing, are discussed in particular. Techniques of electroplating and stencil printing to prepare solder bumping are also described.
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Chip scale package (CSP) for flip-chip on hard substrates and wafer re-distribution is studied, and its process flow is described. Key technologies for CSP, such as structure designing, solder bumping, enveloping, and testing, are discussed in particular. Techniques of electroplating and stencil printing to prepare solder bumping are also described.
Key concepts: Bumping, Chip-scale package, Flip chip, Chip, Thermal copper pillar bump, Wafer, Electroplating, Stencil