2015Dianzi qijianRequires access

The Design of High-Speed Data Acquisition System Based on the USB3.0 Interface

Yue Xiaozhon

Open publisher page 1 citations

Abstract

To meet the problem of current existing in the explosion field measurement memory test system,the data transmission is slow and often lost some data. The high-speed data acquisition system based on USB3. 0 is designed by using the data collection technology,memory test technology and parallel sampling techniques. The system achieved the high-speed parallel data acquisition with two sampling rates of up to 500 Msample / s A / D chip. It can bring the analog signal from the XX Explosion power test field to the FPGA after A / D conversion,and transmit to the PC by the USB3. 0 interface. Data storage can use the time-storage technology. The design method can solved the problem of high-speed transmission and large data storage during the data collection effectively.

About this research paper

What this paper is about

To meet the problem of current existing in the explosion field measurement memory test system,the data transmission is slow and often lost some data. The high-speed data acquisition system based on USB3. 0 is designed by using the data collection technology,memory test technology and parallel sampling techniques. The system achieved the high-speed parallel data acquisition with two sampling rates of up to 500 Msample / s A / D chip. It can bring the analog signal from the XX Explosion power test field to the FPGA after A / D conversion,and transmit to the PC by the USB3. 0 interface. Data storage can use the time-storage technology. The design method can solved the problem of high-speed transmission and large data storage during the data collection effectively.

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Available abstract

To meet the problem of current existing in the explosion field measurement memory test system,the data transmission is slow and often lost some data. The high-speed data acquisition system based on USB3. 0 is designed by using the data collection technology,memory test technology and parallel sampling techniques. The system achieved the high-speed parallel data acquisition with two sampling rates of up to 500 Msample / s A / D chip. It can bring the analog signal from the XX Explosion power test field to the FPGA after A / D conversion,and transmit to the PC by the USB3. 0 interface. Data storage can use the time-storage technology. The design method can solved the problem of high-speed transmission and large data storage during the data collection effectively.

Key concepts: Data acquisition, Interface (matter), Computer data storage, Computer science, Computer hardware, Data transmission, Field-programmable gate array, Sampling (signal processing)

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