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Optimized design of a real-time decoder for MPEG-4 video based on MS320 C6000

Zhaoyan Zhang

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Abstract

In this paper we introduce an implementation of MPEG-4 simple profile video real-time decoder on the TMS320C6000 DSPs. We present some techniques to optimize the decoder which mainly cover the aspects of data structure, memory allocation, data transfer ,software pipeline and decoding timing. On the IDK board of C6711 DSP 150 MHz we are able to demonstrate decoding of MPEG-4 bitstream coded at 800 Kbps, CIF352×288, at a speed of 30～45 fps.

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What this paper is about

In this paper we introduce an implementation of MPEG-4 simple profile video real-time decoder on the TMS320C6000 DSPs. We present some techniques to optimize the decoder which mainly cover the aspects of data structure, memory allocation, data transfer ,software pipeline and decoding timing. On the IDK board of C6711 DSP 150 MHz we are able to demonstrate decoding of MPEG-4 bitstream coded at 800 Kbps, CIF352×288, at a speed of 30～45 fps.

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Available abstract

In this paper we introduce an implementation of MPEG-4 simple profile video real-time decoder on the TMS320C6000 DSPs. We present some techniques to optimize the decoder which mainly cover the aspects of data structure, memory allocation, data transfer ,software pipeline and decoding timing. On the IDK board of C6711 DSP 150 MHz we are able to demonstrate decoding of MPEG-4 bitstream coded at 800 Kbps, CIF352×288, at a speed of 30～45 fps.

Key concepts: Computer science, Decoding methods, Pipeline (software), Bitstream, MPEG-4, MPEG-2, Computer hardware, Digital signal processing

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