2011Power System TechnologyRequires access

Realization of High Accuracy Synchronous Clock for Power System Based on GPS

Peng An

Open publisher page 4 citations

Abstract

In view of the complementarities between the random error of one pulse per second(1PPS) in global positioning system(GPS) and accumulated error of high-precision crystal oscillator,based on the principle of digital phase-locked loop(DPLL) it is proposed to control frequency dividing coefficient of the crystal oscillator second clock by measuring the phase difference between 1PPS of GPS and the crystal oscillator second clock to eliminate the accumulated error of crystal oscillator in real-time mode,thus high-precision 1PPS can be attained and a high accuracy second clock system is designed by use of complex programmable logic device(CPLD).When the reception of GPS is in normal state,a high accuracy second clock can be come into being by CPLD according to the principle of DPLL;when the reception of GPS is in abnormal state,the stored frequency dividing coefficient can be called by CPU to control CPLD to generate high-precision clock signal.Both simulation analysis and experimental results show that the proposed clock system possesses high time accuracy and stability.

About this research paper

What this paper is about

In view of the complementarities between the random error of one pulse per second(1PPS) in global positioning system(GPS) and accumulated error of high-precision crystal oscillator,based on the principle of digital phase-locked loop(DPLL) it is proposed to control frequency dividing coefficient of the crystal oscillator second clock by measuring the phase difference between 1PPS of GPS and the crystal oscillator second clock to eliminate the accumulated error of crystal oscillator in real-time mode,thus high-precision 1PPS can be attained and a high accuracy second clock system is designed by use of complex programmable logic device(CPLD).When the reception of GPS is in normal state,a high accuracy second clock can be come into being by CPLD according to the principle of DPLL;when the reception of GPS is in abnormal state,the stored frequency dividing coefficient can be called by CPU to control CPLD to generate high-precision clock signal.Both simulation analysis and experimental results show that the proposed clock system possesses high time accuracy and stability.

Why it matters

OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

In view of the complementarities between the random error of one pulse per second(1PPS) in global positioning system(GPS) and accumulated error of high-precision crystal oscillator,based on the principle of digital phase-locked loop(DPLL) it is proposed to control frequency dividing coefficient of the crystal oscillator second clock by measuring the phase difference between 1PPS of GPS and the crystal oscillator second clock to eliminate the accumulated error of crystal oscillator in real-time mode,thus high-precision 1PPS can be attained and a high accuracy second clock system is designed by use of complex programmable logic device(CPLD).When the reception of GPS is in normal state,a high accuracy second clock can be come into being by CPLD according to the principle of DPLL;when the reception of GPS is in abnormal state,the stored frequency dividing coefficient can be called by CPU to control CPLD to generate high-precision clock signal.Both simulation analysis and experimental results show that the proposed clock system possesses high time accuracy and stability.

Key concepts: Complex programmable logic device, Crystal oscillator, DPLL algorithm, Clock domain crossing, CPU multiplier, Global Positioning System, Digital clock manager, Clock synchronization

Related papers

Back to paper searchBrowse research topicsOriginal source
Realization of High Accuracy Synchronous Clock for Power System Based on GPS — Research Paper | ScholarLens