High-order FIR filter design on FPGA using MA distributed algorithm

Concerning the problems of too much resource consumption and too low processing speed,a new high-order FIR filter targeted Field Programmable Gate Array(FPGA) was proposed.Firstly,polyphase decomposition architecture and pipeline technology were adopted to decompose high-order FIR filter into low-order ones,and then the proposed MA distributed algorithm architecture was used to implement the decomposed filters in the method.A series of serial and parallel FIR filters which order from 8 to 256 were implemented by ISE10.1 targeted Xilinx Xc2vp30-7ff896 FPGA device.The experimental results show that the proposed method effectively reduces the system resource consumption and improves the timing performance of the system.