Design for testability of deep sub-micro SoC chip

With the improvement of complexity and integration ability of SoC chips,more and more challenges can be encountered in the process of test development.Inhomogeneous system formed by different circuit structures and design styles makes test more difficult,which results in long test time and high test cost.This paper mainly presents the DFT implementation of communication baseband SoC chip.This mix-signal SoC chip comprise analog and digital sub-system,IP cores and embedded on-chip memories.All kinds of test mode could be controlled by on-chip test control unit to accomplish test requirement,supporting traditional scan test for stuck-at fault and scan-based delay test which operated in different clock frequencies and clock domains for delay faults which are more and more common in current deep sub-micro technology,configurable MBIST test mode and other specific DFT techniques.