Optimal Analysis and Simulation of Time Delay in Integrated Circuits

Time delay of N-stage CMOS transmission gate chain and N-gate 3D double-gate SOI IC is optimally analyzed based on Elmore model, and HSPICE simulation results are presented. The study has come to the following conclusions: 1) with each buffer inserted into every other three stages in the N-stage CMOS transmission gate chain, there is minimum delay time; 2) under the same condition as 1 and with N/PMOS device width ratio =3 in every 3-stage, there is also minimum delay time; 3) with m = 6 device-layers for for N-gate 3D DG SOI IC, there is minimum delay time.