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A Data Acquisition System based on NIOS II

Ling Lin

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Abstract

NIOS Ⅱ is the 2nd generation soft IP CPU provided by altera corporation.With other IP cores,they become the main part of SOPC system.User can develop IP core in SOPC design by user-defined logic.It makes the design simply and efficiently.This paper designs a data acquisition system based on NIOS Ⅱ.Using FPGA control the timing of AD7674.It use ping-pong operation to store data temporarily which is achieved by dual-port ram in FPGA.Data are read、stored and sent by NIOS II microprocessor.The data reading is finished by user-defined logic.This system makes the control unit and timing unit designed on one chip.It simplifies the circuit,improves the stability of the system and has good portability.The experimental results provide verification of its good sampling function.

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What this paper is about

NIOS Ⅱ is the 2nd generation soft IP CPU provided by altera corporation.With other IP cores,they become the main part of SOPC system.User can develop IP core in SOPC design by user-defined logic.It makes the design simply and efficiently.This paper designs a data acquisition system based on NIOS Ⅱ.Using FPGA control the timing of AD7674.It use ping-pong operation to store data temporarily which is achieved by dual-port ram in FPGA.Data are read、stored and sent by NIOS II microprocessor.The data reading is finished by user-defined logic.This system makes the control unit and timing unit designed on one chip.It simplifies the circuit,improves the stability of the system and has good portability.The experimental results provide verification of its good sampling function.

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Available abstract

NIOS Ⅱ is the 2nd generation soft IP CPU provided by altera corporation.With other IP cores,they become the main part of SOPC system.User can develop IP core in SOPC design by user-defined logic.It makes the design simply and efficiently.This paper designs a data acquisition system based on NIOS Ⅱ.Using FPGA control the timing of AD7674.It use ping-pong operation to store data temporarily which is achieved by dual-port ram in FPGA.Data are read、stored and sent by NIOS II microprocessor.The data reading is finished by user-defined logic.This system makes the control unit and timing unit designed on one chip.It simplifies the circuit,improves the stability of the system and has good portability.The experimental results provide verification of its good sampling function.

Key concepts: Nios II, Field-programmable gate array, Embedded system, Computer hardware, Data acquisition, Computer science, Software portability, Microprocessor

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