Integration of instruction scheduling and register allocation

Instruction scheduling provides important optimization for current RISC (reduced instruction set computer) processors to achieve high performance by exploiting parallelism. This paper presents an integrated instruction scheduling and register allocation algorithm for processors with an extended delayed-load architecture. The algorithm is based on the delay-load scheduling algorithm using fewer registers and running at a speed proportional to the size of the expression tree. The algorithm also includes some extensions to improve performance: 1) resolve the data dependence of instruction scheduling for multiple expression trees by marking the memory information as changing and by setting a Load Cache; 2) extend the scheduling from expression trees to forests to more effectively reduce delays; 3) effectively reduce structural hazards by adjusting the order of local instructions.