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A Fully Differential Operational Amplifier with Scalable Unit-Gain Bandwidth

Yanju Yang

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Abstract

A fully differential gain-boosted operational amplifier for pipelined ADC was designed.The unit-gainbandwidth of the proposed operational amplifier was scalable with the ADC's sampling rate.So the power consumption of the pipelined ADC at different sampling rate could be optimized,and the efficiency of ADC was improved.The operational amplifier was designed in Chartered 0.18μm CMOS process.The Spectre simulation results showed that the unit-gain bandwidth changed from 117.6 MHz to 495.9 MHz with a capacitive load of 0.5pF as the sampling rate varied from 10 MS/s to 100 MS/s,while the circuit's DC gain and phase margin were reduced slightly.The DC gain was reduced from 115.2dB to 98.7dB,and the phase margin was reduced from78.0°to 74.1°.

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What this paper is about

A fully differential gain-boosted operational amplifier for pipelined ADC was designed.The unit-gainbandwidth of the proposed operational amplifier was scalable with the ADC's sampling rate.So the power consumption of the pipelined ADC at different sampling rate could be optimized,and the efficiency of ADC was improved.The operational amplifier was designed in Chartered 0.18μm CMOS process.The Spectre simulation results showed that the unit-gain bandwidth changed from 117.6 MHz to 495.9 MHz with a capacitive load of 0.5pF as the sampling rate varied from 10 MS/s to 100 MS/s,while the circuit's DC gain and phase margin were reduced slightly.The DC gain was reduced from 115.2dB to 98.7dB,and the phase margin was reduced from78.0°to 74.1°.

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Available abstract

A fully differential gain-boosted operational amplifier for pipelined ADC was designed.The unit-gainbandwidth of the proposed operational amplifier was scalable with the ADC's sampling rate.So the power consumption of the pipelined ADC at different sampling rate could be optimized,and the efficiency of ADC was improved.The operational amplifier was designed in Chartered 0.18μm CMOS process.The Spectre simulation results showed that the unit-gain bandwidth changed from 117.6 MHz to 495.9 MHz with a capacitive load of 0.5pF as the sampling rate varied from 10 MS/s to 100 MS/s,while the circuit's DC gain and phase margin were reduced slightly.The DC gain was reduced from 115.2dB to 98.7dB,and the phase margin was reduced from78.0°to 74.1°.

Key concepts: Fully differential amplifier, Phase margin, Open-loop gain, Operational amplifier, Gain–bandwidth product, Amplifier, Direct-coupled amplifier, Bandwidth (computing)

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