2009Microelectronics & ComputerRequires access

A Single Float-point Singular Value Decomposition Processor Based on FPGA

Dou Heng

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Abstract

A new architecture of single float-point SVD processor is proposed to improve the real-time processing ability in digital signal processing application and compute a large SVD,which is based on the implementation of two-sided Jacobi algorithm on FPGA. This architecture sufficiently considers area-consuming,performance and accuracy,and uses CORDIC unit based on GA algorithm to improve the accuracy and performance of the key module. Moreover,the application of two-plane rotation and FPGA's DSP units farther improves the hardware's performance,and avoids revising the result by scale factor. The experiment demonstrates the proposed architecture is efficient.

About this research paper

What this paper is about

A new architecture of single float-point SVD processor is proposed to improve the real-time processing ability in digital signal processing application and compute a large SVD,which is based on the implementation of two-sided Jacobi algorithm on FPGA. This architecture sufficiently considers area-consuming,performance and accuracy,and uses CORDIC unit based on GA algorithm to improve the accuracy and performance of the key module. Moreover,the application of two-plane rotation and FPGA's DSP units farther improves the hardware's performance,and avoids revising the result by scale factor. The experiment demonstrates the proposed architecture is efficient.

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Available abstract

A new architecture of single float-point SVD processor is proposed to improve the real-time processing ability in digital signal processing application and compute a large SVD,which is based on the implementation of two-sided Jacobi algorithm on FPGA. This architecture sufficiently considers area-consuming,performance and accuracy,and uses CORDIC unit based on GA algorithm to improve the accuracy and performance of the key module. Moreover,the application of two-plane rotation and FPGA's DSP units farther improves the hardware's performance,and avoids revising the result by scale factor. The experiment demonstrates the proposed architecture is efficient.

Key concepts: CORDIC, Computer science, Field-programmable gate array, Digital signal processing, Singular value decomposition, Floating point, Digital signal processor, Float (project management)

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