2009•Unpublished venueRequires access

Design and implementation of FPGA verification platform for a programmable vertex processing unit

Shi Hong-sheng

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Abstract

To process the functional verification and performance evaluation for a programmable vertex processing unit which was designed for mobile devices,a SoPC-based FPGA verification platform was proposed.A number of vertex processing unit programs on the platform had been run using software/hardware co-verification methods.The experimental results show that the verification platform can effectively verify the functions of the vertex processing unit and is suitable for verifying the other modules of the 3D graphics accelerator.

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What this paper is about

To process the functional verification and performance evaluation for a programmable vertex processing unit which was designed for mobile devices,a SoPC-based FPGA verification platform was proposed.A number of vertex processing unit programs on the platform had been run using software/hardware co-verification methods.The experimental results show that the verification platform can effectively verify the functions of the vertex processing unit and is suitable for verifying the other modules of the 3D graphics accelerator.

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Available abstract

To process the functional verification and performance evaluation for a programmable vertex processing unit which was designed for mobile devices,a SoPC-based FPGA verification platform was proposed.A number of vertex processing unit programs on the platform had been run using software/hardware co-verification methods.The experimental results show that the verification platform can effectively verify the functions of the vertex processing unit and is suitable for verifying the other modules of the 3D graphics accelerator.

Key concepts: Field-programmable gate array, Computer science, Vertex (graph theory), Graphics processing unit, Embedded system, Software, Computer hardware, Hardware acceleration

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