A High Performance Code Generator for VLIW Architectures

VLIW architecture is used to enhance the performance of DSP,but also poses a challenge to compiler to generate efficient code for it.As code generation unit of compiler,code generator plays an important role in exploiting VLIW techniques.A code generator based on retargetable compilation infrastructure is proposed and implemented in this paper.It employs the efficient hardware in VLIW structure to greatest extend,supports both SIMD instructions and predication execution,and is able to generate high instruction-level-parallelism assembly code,which greatly improves performance of applications.