Solution to Ambiguities Elimination of VHDL by YAY

A synthesis system based on VHDL usually consists of parser, optimizer and inferencer. The parsers of some existing VHDL synthesis systems are commonly generated by YACC. However, VHDL definitions have many ambiguities, the codes of grammar description of VHDL with YACC are low efficient because many measures must be adopted to avoid conflicts in parsing. In this paper, a new technique to generate a VHDL parser by YAY, another kind of compiler generator, is introduced. When using YAY, programmers can solve the problem of ambiguity elimination easily.