Design and Implementation of Optimal Digital Filter

A new structure of FPGA based optimal finite impulse response(FIR) filter is presented in this paper. FPGA hardware realization of parallel DA, series DA and series-parallel DA has been studied. After analyzing the advantages and disadvantages of various forms of structural, a 128-step constant coefficient optimal FIR filter is designed, which will reduce the hardware resource and improve the compute speed. An FPGA chip of the CycloneIII is adopted to achieve the processor and VHDL language is used in program. At last, amplitude frequency characteristic is tested by Network Analyzer. Simulation results demonstrate the effectiveness and real time property of the algorithm.