Exploration of Experiment Teaching of Digital Logic

Aimed at the problems in experiment teaching of digital logic, the idea of reforming experiment teaching of digital logic and designing experiment task is proposed in this paper. The traditional test-and-verify experiments are replaced with design experiments of VHDL. The design of experiment tasks and the teaching effect are introduced. The experiment tasks should be the major point of knowledge and in appropriate difficulty and no existing answer. The experiment tasks include two combinational logic design and three sequential logic design tasks. There are basic experiments and optional experiments as well. The teaching effect shows that the design of experiment tasks is successful, and the anticipating aim is achieved.