Translation lookaside buffer design based on dynamic memory page merging

Virtual memory pages and physical memory pages are often sequentially allocated in traditional memory management algorithms.A translation lookaside buffer(TLB) design method was proposed to merge two sequential small size memory pages into a large one during the processor execution.The mapping size of each TLB entry is automatically enlarged with recursive memory page merging.Consequently,the utilization efficiency of TLB can be improved and the TLB miss rate can be reduced.A new uTLB architecture composed of fuTLB and suTLB was proposed.Both fuTLB and suTLB are not only used as the first level address translation buffer of the two-level TLB architecture,but also provided as the temporary buffer for hardware based dynamic page merging.The page merging operation is processed by hardware and not affected by software.Experimental results from Mibench show that the TLB miss ratio can be reduced by 27% with the new TLB design method compared with the filter-TLB design method.