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Synchronous Reset and Asynchronous Reset in ASIC Design

Liu Zhi-ju

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Abstract

Reset is one of the key problems in ASIC design, it will directly influence the performance of the whole design if it is done properly or not. This paper discussed and analyzed the synchronous reset and the asynchronous reset from several different perspectives. A Comparison between them in the advantages and the disadvantages was conducted. The metastability problem, exiting in the process of asynchronous reset, was resolved by adding the two-level reset synchronizer logic and using reset distribution buffer tree.

About this research paper

What this paper is about

Reset is one of the key problems in ASIC design, it will directly influence the performance of the whole design if it is done properly or not. This paper discussed and analyzed the synchronous reset and the asynchronous reset from several different perspectives. A Comparison between them in the advantages and the disadvantages was conducted. The metastability problem, exiting in the process of asynchronous reset, was resolved by adding the two-level reset synchronizer logic and using reset distribution buffer tree.

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Method / approach

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Available abstract

Reset is one of the key problems in ASIC design, it will directly influence the performance of the whole design if it is done properly or not. This paper discussed and analyzed the synchronous reset and the asynchronous reset from several different perspectives. A Comparison between them in the advantages and the disadvantages was conducted. The metastability problem, exiting in the process of asynchronous reset, was resolved by adding the two-level reset synchronizer logic and using reset distribution buffer tree.

Key concepts: Reset (finance), Synchronizer, Asynchronous communication, Computer science, Application-specific integrated circuit, Key (lock), Process (computing), Computer hardware

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