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A CMOS Operational Amplifier with High PSRR

Ruzhang Li

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Abstract

The reason why the conventional basic two-stage CMOS operational amplifier has a low PSRR was analyzed.A method to improve PSRR only by modifying bias structure was presented.The opamp was simulated based on 0.35 μm standard CMOS technology in Cadence environment.Results showed that the circuit had a 20 dB increase in PSRR over a wide range of frequencies,compared with the conventional basic two-stage CMOS opamp.

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What this paper is about

The reason why the conventional basic two-stage CMOS operational amplifier has a low PSRR was analyzed.A method to improve PSRR only by modifying bias structure was presented.The opamp was simulated based on 0.35 μm standard CMOS technology in Cadence environment.Results showed that the circuit had a 20 dB increase in PSRR over a wide range of frequencies,compared with the conventional basic two-stage CMOS opamp.

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Available abstract

The reason why the conventional basic two-stage CMOS operational amplifier has a low PSRR was analyzed.A method to improve PSRR only by modifying bias structure was presented.The opamp was simulated based on 0.35 μm standard CMOS technology in Cadence environment.Results showed that the circuit had a 20 dB increase in PSRR over a wide range of frequencies,compared with the conventional basic two-stage CMOS opamp.

Key concepts: Power supply rejection ratio, Operational amplifier, CMOS, Electronic engineering, Electrical engineering, Cadence, Engineering, Computer science

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