Realization of CIC filter based on FPGA

Directed at overcoming the pressure on DSP computation exerted by huge data quantity due to intermediate frequency sampling in the baseband in software radio system,the paper introduces the use of the technique of sample rate conversion in the receiver/sender and cascade integrator comb(CIC) filter to realize digital sampling rate conversion.The method can fulfill the requirement of anti-aliasing effects.This paper is focused on the normal methods and the modified methods to realize 5-stage CIC filter.The result of experiments shows that in the case of 5-stage CIC filter,normal methods operate at the greatest frequency of 160 MHz,using 228 logic elements;the modified methods at the greatest frequency of 193 MHz,using 225 logic elements.Both methods are verified to be valid by timing simulation with Quartus II.The modified methods prove to be more suitable for multi-rate high-speed signal processing system.