2003Journal of Information Engineering UniversityRequires access

Hardware Architecture for Fast Decoding Implementation of Errors-and-Erasures Correcting Reed-Solomon Codes

LI Shui-ping

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Abstract

In this paper the authors first introduce fundamental theory of RS decoding,describe the novel Inverse-Free Berlekamp-Massey decoding algorithm for Reed-Solomon Codes, and develop this decoding algorithm.Finally,the authors apply the developed algorithm for Errors-and-Erasures correcting Reed-Solomon decoding, and give the hardware architecture for decoding implementation.

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What this paper is about

In this paper the authors first introduce fundamental theory of RS decoding,describe the novel Inverse-Free Berlekamp-Massey decoding algorithm for Reed-Solomon Codes, and develop this decoding algorithm.Finally,the authors apply the developed algorithm for Errors-and-Erasures correcting Reed-Solomon decoding, and give the hardware architecture for decoding implementation.

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Available abstract

In this paper the authors first introduce fundamental theory of RS decoding,describe the novel Inverse-Free Berlekamp-Massey decoding algorithm for Reed-Solomon Codes, and develop this decoding algorithm.Finally,the authors apply the developed algorithm for Errors-and-Erasures correcting Reed-Solomon decoding, and give the hardware architecture for decoding implementation.

Key concepts: Berlekamp–Welch algorithm, Decoding methods, List decoding, Sequential decoding, Reed–Solomon error correction, Computer science, Algorithm, Error detection and correction

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