Realization of CIC Decimation Filter Gain Correction in Application of FPGA

In IF digital signal processing,the applications of FPGA are used more widely.DDC FPGA modular is necessary.Since its structure uses only adders and delayers,a CIC filter is achieved suitable for FPGA.CIC filters usually work in the first level with large amount of computation in DDC system.This paper first analyzes the theory,performance,impact parameters and gain generation reason of the CIC filter,for the problem that gain generated when five stages CIC decimation filter works under different decimation rates in practical application,and then gives the method of gain correction.Finally,it is verified in Modelsim Simulation.