Yin Wei-han
Abstract
A NIOS Ⅱ-based method for decoder design was proposed to have the SOPC adopted,the FPGA and interface circuit employed and an embedded NIOS Ⅱ CPU integrated into FPGA to form the system on chip(SOC),and then have the serial code transformed into a 8-bit side-by-side code and the decoding result displayed through a host computer software.
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A NIOS Ⅱ-based method for decoder design was proposed to have the SOPC adopted,the FPGA and interface circuit employed and an embedded NIOS Ⅱ CPU integrated into FPGA to form the system on chip(SOC),and then have the serial code transformed into a 8-bit side-by-side code and the decoding result displayed through a host computer software.
Key concepts: Nios II, Field-programmable gate array, Embedded system, Decoding methods, Computer science, Chip, Code (set theory), Computer hardware