2006•Huadong Shifan Daxue xuebao. Ziran kexue banRequires access

Design of I~2 C-Bus Interface Based on SpartanIIXC2S100

HU Wen-jing, LI Wai-yun

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Abstract

The protocol and principle of I~2 C-Bus were introduced.The framework of I~2 C-Bus based on FPGA was proposed.The idea of nesting state-machine of complicated timing-circuit and the hardware description of I~2 C-Bus interface by Verilog HDL were presented.The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I~2 C device based on SpartanⅡXC2S100 was implemented.

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The protocol and principle of I~2 C-Bus were introduced.The framework of I~2 C-Bus based on FPGA was proposed.The idea of nesting state-machine of complicated timing-circuit and the hardware description of I~2 C-Bus interface by Verilog HDL were presented.The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I~2 C device based on SpartanⅡXC2S100 was implemented.

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Available abstract

The protocol and principle of I~2 C-Bus were introduced.The framework of I~2 C-Bus based on FPGA was proposed.The idea of nesting state-machine of complicated timing-circuit and the hardware description of I~2 C-Bus interface by Verilog HDL were presented.The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I~2 C device based on SpartanⅡXC2S100 was implemented.

Key concepts: ModelSim, Verilog, Field-programmable gate array, Interface (matter), Computer science, Embedded system, Back-side bus, State (computer science)

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