Cooperating Global Instruction Scheduling and Instant Register Allocation

Instruction Level Parallelism (ILP) is an important characteristic of current high performance processor. Compiler has critical impact on how to make full use of the strong parallel processing ability of this kind of processor. With the background of developing an ILP compiler for a VLIW like processor, this paper discusses the kernel problem of ILP compilation global instruction scheduling and register allocation, introduces the phase ordering problem faced the design of the back end of this compiler, and presents the cooperated global instruction scheduling and register allocation method as a solution.