The Realization of Polyphase Decimation Filter on FPGA

Polyphase decomposition played an important role in multi-rate signals processing.The paper introduced the polyphase decomposition theory,combined with the polyphase decomposition form of the FIR decimation filter,realized 2 times polyphase structure decimation filter with Verilog HDL,simulated waveform by Quartus,verified the result and compared it with the theory value by MATLAB,which was correct.Finally,the programmable file was downloaded to FPGA.The design method of polyphase decimation filter was feasible;the entire design process was realized by software,easy to modify the parameter.