Hardware Design and Algorithm Optimization of Video Encoder Based on DSP and FPGA Techniques

With the development of video encoding techniques, video compression algorithms become more complicated. A real-time high resolution video encoder cannot be implemented with a single CPU or DSP. A MPEG-4 video encoder is designed and implemented based on coordinated DSP and FPGA techniques. The FPGA module takes the tasks of video acquisition, YUV separation and data I/O functions, while the DSP is dedicated for video compression. The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP′s on-chip memory. A Macro Block (MB) type judging algorithm is proposed based on MB′s space complexity. It reduces effectively the computational complexity of the video compression. The experimental results indicate that the MPEG-4 video encoder implementation can encode 39.2 f/s in CIF resolution.