Design of GPS/GSM vehicle monitoring system terminal based on NIOS II processor

It was taken very short time to integrate NIOS II CPU, the Avalon address lines, the interfaces of peripherals and memories and the inner debug module into the requisite NIOS II processor using the SOPC Builder. Then it needed to use the Quartus II design software to combine NIOS II processor with GPS interface, GSM interface and other peripheral interfaces, finishing the hardware design by compiling and downloading it into the FPGA chip. The software was usually writed with C or C++ language and to be compiled and downloaded into FPGA by NIOS II IDE.