A 12-bit high-speed DAC based on self-calibration technique

In this paper,an analog self-calibration technique is introduced to improve the linearity of DAC (Digital-to-Analog Converter),and is compared with DEM (Dynamic Element Matching). Such self-calibration technique is implemented also in a high-speed design using the Infineon 0.25μm CMOS process. In the 4-bit DAC design,with the supply voltage of 1.8V,at the sampling frequency of 400MHz. SNDR (Signal to Noise and Distortion Ration) achieves 76dB,over 12 bits in ENOB (Effective Number of Bits),which is 3bit higher than that without calibration technique,SFDR (Spurious Free Dynamic Range) reaches 84.66dB,and Glitch Energy is lower than 3fA-s.