The Design and Implementation of a Effective Prefetch Mechanism

We present a new model of prefetching in the design of the NCS processor. This model make full use of the multi－ phase clock to control the prefetching of instructions and data. It effectively diminish the bottle－ neck of the access of memory. This model has tested to be effective by applying it on some testbench. We also give out the circuit of the model and it is important to the designing of the processor with our own copyright.