Design and implementation of Parallel Prefix Adders using FPGAs

Adders are known to have the frequently used in VLSI designs.In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders.RCA use to perform any number of addition.In this RCA is serial adder and it has commutation delay problem.If increase the ha&fa simultaneously delay also increase.That's why we go for parallel adders(parallel prefix adders).IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder.These adders are designd and implemented on FPGA sparton3E kit.Simulated and synthesis by model sim6.4b,Xilinx ise10.1.