Digital Technique for Analog Built-in Self-Test

A device core logic testing of analog signals with minimal area overhead for measuring on chip voltages in digital circuits can be adopted by built-in-self-test in a distributed architecture.Here for measuring this analog voltage, the subsampled signal pair is fed to delay measurement to measure the skew between this pair.The routing of analog signals over long paths can be minimized by using clock gating.A clock is routed serially to the nodes of analog test voltage with consists of delay cells, flipflops.However the test voltage to a scheme between pair of signals raise to the signal pair at node.