An Impedance Analysis of Multiple Decoupling Capacitors with Series Resistors.

It is known that multiple decoupling capacitors with series resistors, which can prevent impedance from increasing at the anti-resonance frequency, are effective for noise reduction at higher radio frequencies. Clock speed of a digital circuit now often exceeds 100MHz. Therefore, 3 or more decoupling capacitors are neccesary to reduce the radiation noise from such digital circuits. But in case of 3 decoupling capacitors with series resistors connected in parallel, it is impossible to solve the five-degree impedance equation analytically. The optimum value of the resistor to minimize the impedance is found with a circuit simulator and the results were convinced by measurements.