Implementation of Overlap based Logic cell andits Power Analysis

This Paper deals with power-efficient architecture of static/dynamic edge triggered flip flops with clock Overlap-based logic. Clock overlap is the major issue in sequential circuits. The Overlap based Logic cell is more efficient in terms of power consumption and have acceptable overlap periods when compared to other dynamic/static logic architectures. When compared to conventional dynamic logic method, the proposed logic style consumes low power. The result of this logic is that static power consumption gets improved in CMOS technology. Finally the power comparison is done between the overlap logic and conventional dynamic C2MOS logic. Low Power utilization is analyzed using Cadence tool and technology used is 180nm GPDK technology