Design of SRAM Cell by Using Self- Controllable Voltage Level Circuits

Memory is the most common part in CMOS applications. The power consumption and speed are important issue that has led to multiple designs with the purpose of minimizing the power during both read and write operations of SRAM .In modern high performance integrated circuits more than 40% of the total active mode energy is consumed due to leakage currents. The feature size of the transistor is scaled down the threshold voltages of MOSFETs have been reduced thereby increasing leakage power substantially. Leakage is the only source of energy consumption in an idle circuit .SRAM arrays are important sources of leakage since the majority of transistors are utilized for onchip memory in today‟s high performance microprocessors and systems-on-chips. A new leakage current reduction circuit called improved Self-controllable Voltage Level (SVL) circuit is developed and included to reduce the leakage power of 6T SRAM. Simulation result of 6T SRAM with improved SVL design using TANNER tool shows the reduction in total average power and delay.