Evaluation of Sub-threshold Digital Circuits for Wireless Communication Systems

Digital circuit designs in sub-threshold region have been studied in recent years. Their works rely on special purpose CMOS cell library with various voltage conditions for the purpose of adjusting circuit delays. This paper proposed modeling analysis for each typical CMOS logic cell to operate at sub-threshold region. Critical-path delays and power dissipation will be analyzed in strong and weak inversion by considering scale factors from typical to sub-threshold voltage conditions. We evaluated wireless circuits in orthogonal frequency division multiplexing (OFDM) communication receiver. The simulation results clearly show that low voltage is not a barrier for large-scale digital circuits.